RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design by Sutherland, Stuart

RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

$103.99 $120.00

Discount: $16.01 (14%)

Hurry Up! Only 171 Left in Stock!

Out of stock >
Guarantee safe & Secure checkout
visamasteramerican expressshopify paypaypalgoogle pay

In Stock

Contributors:
Binding:
Paperback
Book Subcategory:
Book Topic:
img
Shipping & Return +
The product is eligible for a complimentary return within 30 days from the date of purchase. Furthermore, individual items are shipped within 24 hours of receiving the order.
img
Rating and Reviews +
img
Specifications +
Release Date:
2017-06-10
ISBN 13:
9781546776345
Weight:
1.42 lbs
Size:
9.00 x 6.00 x 0.98 inches
Pages:
488
img
Mint Condition +

product description

Have a question?